A variety of methods have been developed for creating patterned masks suitable for patterning underlying materials during fabrication of integrated circuitry. A continuing goal of integrated circuit fabrication is to increase integrated circuit density, and accordingly to decrease the size of individual integrated circuit components. There is thus a continuing goal to form patterned masks having reduced feature sizes.
A typical patterned mask utilized for integrated circuit fabrication is photolithographically-patterned photoresist. Such may be utilized to form feature sizes approaching about 40 nanometers (nm). Sublithographic feature sizes may be formed utilizing pitch-multiplication methodologies (which reduce pitch size by a given multiple; for instance, pitch-doubling methodology reduces pitch size by a multiple of two). However, pitch-multiplication methodologies may be costly due to the complexities associated with such methodologies. Another method showing promise for creating sublithographic feature sizes involves self-assembly of block copolymer to form repeating patterns. Unfortunately, there is often poor control of the final pattern created with the block copolymer. Accordingly, there may be too many defects remaining in the final pattern for commercial viability.
It is desirable to develop new methods for patterning sublithographic features suitable for semiconductor fabrication.